verilator

all

Convert Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling.

Examples (4)

Build a specific C project in the current directory

verilator --binary --build-jobs 0 -Wall path/to/source.v

Create a C++ executable in a specific folder

verilator --cc --exe --build --build-jobs 0 -Wall path/to/source.cpp path/to/output.v

Perform linting over a code in the current directory

verilator --lint-only -Wall

Create XML output about the design (files, modules, instance hierarchy, logic, and data types) to feed into other tools

verilator --xml-output -Wall path/to/output.xml